all power definitions must exist in netlist and all device models must be defined in the device file. Device definitions may be differentiated by parameters (e.g. L>100nm).

Different metal masks may be created by using metal switches (resistors or capacitors in the netlist). For normal simulation, a different netlist is required for each mask. However, both mask configurations can be verified with one netlist using CVC by changing the switch definitions in the device file. Nets shorted via switches are considered to be the same net.

mosfets that are always on because the max gate voltage ＜max source voltage for pmos, or the min gate voltage＞ min source voltage for nmos.

VDD＜VCC
PMOS is always on

VSS＞VBB
NMOS is always on

all shorts between power signals are reported and other shorts (input, internal nets) are reported if the current exceeds a specified limit.

generally, this indicates a missing power definition.

Mosfet error where the source and drain are connected to different power nets and the gate level is indeterminate. This is a potential intermittent error that is not readily detectible by other programs.

Short only
when input is high

Also detects
these errors

logically undriven gates.

Hi-Z input but
no leak path
therefore no error

Hi-Z input
with leak path
therefore error

detected if the maximum voltage difference exceeds the specified tolerance for each device/terminal combination. For mosfets, the gate-source, source-drain, source-bulk, gate-bulk checks are all possible.

expected values can be set for minimum, maximum, and simulation voltages. An error is generated if the calculated value does not match the expected value. It is possible to expect undriven (open) nets.